| 摘要 |
A data decoder, for example, for decoding teletext and VPS data, comprises an input signal clamp and synchronizing signal separator circuit which receives a combined video and blanking signal and produces synchronizing pulses for a timing circuit and video signals which are applied to an ADC and a data slicer and clock regenerator (DSCR). Sliced data and clock signals feed an acquisition circuit which acquires selected data which is stored in a memory via a memory interface. A control circuit is arranged to modify the DSCR, acquisition circuit and memory interface dependence upon the type of data detected. The arrangement decoder is set to decode data of one type, for example, teletext, and if no valid teletext data is detected within a given period, for example, four television frames, the control circuit causes the decoder to attempt to decode data of the other type (VPS).
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