| 摘要 |
<p>PURPOSE:To suppress a circuit scale small and to reduce power consumption by synchronously operating a decoding processing circuit, a display processing circuit and various processing circuits constituting the decoding processing circuit. CONSTITUTION:A timing unit 18 generates plural timing control signals for instructing the respective operation timings of an input buffer memory 11, a decoding buffer memory 12, a variable length decoding unit 13, an IQ.IDCT unit 14, a movement compensation unit 15, a display unit 16 and a memory controller 17 for constituting a decoder LSI 1 from inputted vertical synchronizing signals, horizontal synchronizing signals and clock signals. That is, the respective timing control signals are generated corresponding to a fixed time slot predetermined for a display timing. Then, the decoding processing circuit, the display processing circuit and the various processing circuits for constituting the decoding processing circuit are synchronously operated. Thus, a timing circuit for generating the timing signals of the fixed time slot can be a simple circuit.</p> |
