发明名称 |
Image processor memory for expediting memory operations |
摘要 |
An electronic data storage memory performs logic operations on the data values existing in its storage cells to eliminate the number of necessary memory accesses during bitblts. The time in which a bitblt can be completed in an image processing system is prolonged because of the number of memory cycles performed during a "raster operation". Thus, to reduce the number of necessary memory cycles, simple logic operations are performed in image processor memory so that a raster operation may take place without having to read, for example, the destination operand from memory. Since a bitblt performs a raster operation on each pixel in the bitblt block, the reduction in memory access time is proportional to the size of the bitblt block.
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申请公布号 |
US5487051(A) |
申请公布日期 |
1996.01.23 |
申请号 |
US19940210355 |
申请日期 |
1994.03.18 |
申请人 |
NETWORK COMPUTING DEVICES, INC. |
发明人 |
PROVIDENZA, JOHN R.;BOEKELHEIDE, LEE |
分类号 |
G06T1/60;G11C7/10;(IPC1-7):G11C13/00 |
主分类号 |
G06T1/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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