发明名称 Fast synchronization of asynchronous signals with a synchronous system
摘要 A method and apparatus provides fast synchronization of asynchronous signals to use by a synchronously operated device by quantizing the delay of an input clocked bistable device which receives and stores the asynchronous signal in response to a first synchronous clock pulse so that such input clocked bistable device has a metastable time period which is less than a predetermined maximum delay period. The output signal of the input clocked bistable device is connected directly to as an input to an asynchronously operated logic circuit part selected to provide a resulting output signal corresponding to the result of performing a logical operation on the output signal within a predetermined minimum time period. The resulting output signal is directly applied to the input of another synchronously operated bistable device which stores the resulting output signal in response to the next occurring synchronous clock pulse corresponding to a time period which is greater than the time of the metastable time period, minimum delay of the logic part and preset of time of such bistable device.
申请公布号 US5487163(A) 申请公布日期 1996.01.23
申请号 US19930148030 申请日期 1993.11.04
申请人 BULL HN INFORMATION SYSTEMS INC. 发明人 KEELEY, JAMES W.
分类号 H03K5/135;(IPC1-7):H03K5/13;H03K19/003 主分类号 H03K5/135
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