| 摘要 |
Communication networks for integrated circuits such as programmable logic devices have a plurality of input conductors each of which is connected to two output multiplexers. For good signal routability through the network, no two multiplexers are connected to the same two input conductors. The girth of the multiplexer allocation graph associated with the network is four, and the graph is preferably a highly regular structure known as a cage or a regular structure derived from a cage. The input conductors are assigned to the edges in this regular graph in such a way that a highly regular pattern of connections between the input conductors and the multiplexers results to facilitate physical implementation of the network in the integrated circuit.
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