| 摘要 |
<p>PURPOSE:To count up even a high clock frequency by composing an adder of a first adder for calculating the low-order part of addition, second adder for calculating the high-order part of addition, and the selector of carry signal control for the high-order part and the low-order part to input the output of the second adder. CONSTITUTION:An adder 1 calculates the low-order part with an m-bit adder 2 for adding '1' and calculates the high-order part with a selector 6 for controlling it by the carry signal of the low-order part by inputting a value calculated by an n-m bit pipeline adder for adding '1' and the output high-order part of a register 5. Concerning the low-order part, adding processing is performed to add '1' to the last value by one clock. Since the adder of the adder 1 is '1', all the adders are '0' excepting for the least significant bit of '1' and the high-order part becomes the last value or a value adding '1' to the last value only when there is carry from the low order. Concerning the low-order part, the carry signal is periodically generated once 2 times. During it, the value inputted to the high-order adder is not changed but when carry occurs, the high-order adder completes the arithmetic.</p> |
