LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT,申请号JP19940150967-传众专利搜索

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发明名称	LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要
申请公布号	JPH0816649(A)	申请公布日期	1996.01.19
申请号	JP19940150967	申请日期	1994.07.01
申请人	FUJITSU LTD	发明人	NIIYAMA SHINYA
分类号	H01L21/82;G06F17/50;(IPC1-7):G06F17/50	主分类号	H01L21/82
代理机构		代理人
主权项
地址

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