| 摘要 |
PURPOSE:To obtain a test mode setting circuit in which a test mode can be set at one outer terminal by employing normal operation clock and reset signal commonly in a test mode control signal generation circuit provided in an LSI. CONSTITUTION:JKFFs 11-14 generate test mode setting codes and a test mode decode section 15 decodes a count holding the test mode setting codes to generate test mode control signals T1-T16. A clock signal outer input terminal 16 is connected with the CK terminal of the FF 11 and the CK terminal of the FF 12-14 is connected with the Q terminal of a prestage FF. Reset outer input terminal 17 and main control signal outer input terminal 18 are connected, respectively, with the reset terminals J, K of the FFs 11-14. These signal inputs are employed for controlling the test mode setting circuit to generate the signals T1-T16. In other words, the operation clock and reset signal are shared by the FFs 11-14 and the normal operation terminals 16, 17 and a test mode setting code is generated by a control signal delivered from one dedicated terminal 18. |
