发明名称 COPROCESSOR SYSTEM AND EXTERNAL MEMORY DEVICE WITH AUXILIARY OPERATION FUNCTION
摘要 <p>PURPOSE:To improve the processing efficiency by enabling a C-CPU and an S-CPU to access an M-ROM practically simultaneously (dual phase) without increasing the memory capacity. CONSTITUTION:A gate system 10 includes an S-CPU 18 of a game machine main body 12 and a C-CPU 34 of a cartridge 14, and CPUs 18 and 34 consist of the same CPU core and have the same memory mapping. The access time of an M-ROM 22 of the cartridge 14 is shorter than the cycle time of the C-CPU 34, and the cycle time of the C-CPU 34 is shorter than that of the S-CPU 18. The period when the access from the S-CPU 18 to the M-ROM 22 is permitted by a signal SSYNC is longer than th8 access time of the M-ROM 22 and is shorter than the cycle time of the S-CPU 18. Consequently, the access from the C-CPU at to the M-ROM 22 is permitted in a margine time by the signal SSYNC.</p>
申请公布号 JPH0816530(A) 申请公布日期 1996.01.19
申请号 JP19940152508 申请日期 1994.07.04
申请人 KURIEITEIBU DESIGN:KK;NINTENDO CO LTD 发明人 TAKAHASHI TOYOFUMI;TANAKA TOSHIO;TERAKAWA HIDEAKI
分类号 G06F9/38;G06F9/50;G06F15/17;(IPC1-7):G06F15/16 主分类号 G06F9/38
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