Dynamic semiconductor memory with memory cell field

摘要

The field of the memory cells forms a matrix with lines and columns. It has an input for a first control signal (RAS) activating the DRAM. An address input (6) receives an address signal (A0-A7) for energising one memory cell. A signal generator (5') forms an internal address signal (RAn) in response to the address signal at the address input, if the first control signal assumes an inactive state.Pref. the address signal generator is a line buffer and generates an internal line address signal for energising a line of memory cells. A decoder (4') processes the address signal, while a first control generates a second control signal (RAE) in response to the first control signal