发明名称 |
Self-aligned anti-punchthrough implantation process |
摘要 |
The invention relates to a method of forming an improved MOSFET device structure for use in ultra large scale integration devices. A local self-aligned anti-punchthrough region is formed directly under the gate electrode using ion implantation. The local anti-punchthrough region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local anti-punchthrough region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. Channel mobility is not degraded and the source and drain junction capacitances are reduced. The invention can be used in either N channel or P channel MOSFET devices, and in either LDD (light doped drain) or non-LDD devices.
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申请公布号 |
US5484743(A) |
申请公布日期 |
1996.01.16 |
申请号 |
US19950394587 |
申请日期 |
1995.02.27 |
申请人 |
UNITED MICROELECTRONICS CORPORATION |
发明人 |
KO, JOE;HSUE, CHEN-CHIU |
分类号 |
H01L21/336;H01L29/10;H01L29/78;(IPC1-7):H01L21/265 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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