| 摘要 |
A response stack validation checking circuit for providing a hardware based approach for monitoring the integrity of a read and a write pointer in a memory stack. The present invention may be utilized in systems having a common memory controller for controlling the read and write pointers or a system having a number of asynchronous memory controllers, wherein each controller controls a different pointer. The present invention allows the memory controller elements to be less complex than a software based approach and therefore may reduce the physical space and power required by the memory controllers. Finally, the present invention may monitor the integrity of the read and write pointers in parallel with the memory controllers and in real time thereby not slowing down system performance.
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