Integrated circuit having a control signal for identifying coinciding active edges of two clock signals

摘要

A data processing system receives a CLK signal for performing operations internal to a data processor (10). The data processor (10) has a CPU (12) which performs operations in response to the CLK signal. The bus is allowed to operate at a frequency which is less than or equal to the operational frequency of the CLK. The bus clock is typically either equal to the clock in frequency or runs at one-half or one-quarter speed. A CLKEN* signal input to the processor (10) is asserted to indicate an active edge of the external bus clock and synchronize the active edge of the external bus clock with an active edge of CLK to allow an active edge of CLK to perform bus operations which coincide with the active edge of the external bus clock. In another form, an internal counter/control circuit (20) may be used internal to the processor (10) to generate internal CLKEN* signals.