| 摘要 |
<p>PURPOSE:To provide a flip flop circuit for testing scanning path which can minimize the area increase of a circuit while reducing the occurrence of delay simulation errors. CONSTITUTION:A flip flop circuit for testing scanning path is constituted of a selector circuit 55 which selects data signals from a data input terminal 51 inverted through such a logic circuit 54 as the inverter circuit, etc., and scan signals from a scan signal input terminal 52 based on a scan testing mode switching signal from a scan mode switching input terminal 53 and a D-flip flop circuit 56 which latches and outputs the output of the circuit 55 in accordance with a clock signal. Since the logic circuit 54 is provided, the input impedance at the data input terminal 51 can be increased and the occurrence of delay calculation errors can be reduced at the time of performing delay simulation.</p> |
