发明名称 PARALLEL DECODER OF DIGITAL VIDEO SIGNAL
摘要 <p>PURPOSE: To effectively perform a parallel, processing by processing one macro block by dividing it into four sub-blocks when compressed video data is decoded. CONSTITUTION: A variable length encoded conversion coefficient and a motion vector are decoded, conversion coefficient data is transmitted to an inverse jigzag scanner 120 and motion vector data is simultaneously transmitted to respective motion conpensation units 330, 430, 530, 630 incorporated in a video data processing module in a VLD circuit 100. The video data is given from the circuit 100 to the scanner 120, a block of a quantized DCT coefficient is converted into one set of the DCT coefficients by a reverse quantization device 140, simultaneously given to a reverse discrete cosine conversion IDCT circuit 160, where a frame differential signal between the block of the present frame and the block corresponding to the previous block are transmitted to a video data dividing circuit 180 and divided. On the other hand, the variable length encoded motion vector from the circuit 100 is given to the respective motion compensation units and sectioned macro block data is processed.</p>
申请公布号 JPH089389(A) 申请公布日期 1996.01.12
申请号 JP19950171410 申请日期 1995.06.14
申请人 DAIU DENSHI KK 发明人 IN SAISHIYU
分类号 H04N19/50;G06T1/00;G06T9/00;H03M7/36;H04N19/102;H04N19/139;H04N19/42;H04N19/423;H04N19/436;H04N19/44;H04N19/46;H04N19/463;H04N19/503;H04N19/51;H04N19/517;H04N19/57;H04N19/61;H04N19/625;H04N19/70;H04N19/91;H04N19/93;(IPC1-7):H04N7/32 主分类号 H04N19/50
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