| 摘要 |
PURPOSE:To reduce the power consumption at the time of multiplier-fixed multiplication. CONSTITUTION:One digit Z1 of a partial product is outputted by performing logical operation by inputting a shift signal C1 obtained by performing the booth decoding of two adjacent digits Xi-1 and Xi of a multiplicand and three adjacent digits of a multiplier, an inverted signal C2, and an enable signal C3. Respective elements other than TGs 2 and 3 have CMOS structure. When an enable signal C3 is 0, a NAND 6 outputs 1, so 0 is always outputted as Zi. At this time, an AND 4 always outputs 0, so when the Ki-1 and Xi vary, neither the outputs of the NAND 6 and an INV 7 nor the output of the EXOR 5 varies. For the purpose, the multiplier-fixed multiplication is performed and when the enable signal C3 is 0, the electric power loss accompanying the operation of those elements is reduced. Consequently, the power consumption at the time of the multiplier-fixed multiplication is reduced. |
