| 摘要 |
The circuit has data receiving circuitry (6) to receive data items from a signal (RXD) co-ordinated by a predetermined timing signal (SCK2) (pref. a serial pulse clock signal). A time differing element (I,8) (pref. including circuitry (I) to invert the timing signal) provides a different time (SCK3) for operation of the data receiving circuitry. The received signal successively transmits the data items maintaining each for a predetermined time period (pref. between two adjacent similar edges of the clock). The time differing circuit provides its different time by delaying for a period within the data period. |
