| 摘要 |
<p>PURPOSE:To eliminate the influence of interference nioses between bit lines at the time of writing and readout by selecting bit line pairs and bit line pairs holding there between the bit line pairs connected respectively with NAND memory cells by a first and a second switching parts and connecting them with sense-amplifiers. CONSTITUTION:NAND memory cells selected with word lines WL10, WL11... and bit line pairs BL11 and BL12, BL13 and BL14... are connected with sense- amplifiers SA11, SA12.... In this case, bit line pairs BL11 and BL12... are selected by the first switching parts Q21, Q22... and adjacent bit line pairs BL12 and BL13, BL14 and BL15... holding there between bit line pairs BL11 and BL12, BL13 and BL14..., etc., are selected by the second switching parts Q41, Q42 to be connected with sense-amplifiers SA11, SA12.... By these connections, the influence of the interference noises between bit lines at the time of the writing and the readout is eliminated and an operating margin is enlarged.</p> |
