| 摘要 |
<p>A digital oscillator (11) is synchronized to a master clock by comparing the master clock to an output of the digital oscillator (11) by providing both to a first register (15) which enables a counter (16). The counter (16) increments while enabled until cleared. The output of the counter (16) is then compared with a stored signal. Depending upon the match with the stored signal, the output of the digital oscillator (11) is either slowed, advanced or maintained. The output from the digital oscillator (11) is then fed back to an input of the digital phase locked loop (10).</p> |
