| 摘要 |
<p>The invention is a static VAR compensator (SVC) (18) which provides optimized power factor correction in the presence of resonant line conditions and large amplitude harmonics. A gate drive signal is applied to the solid state devices (21) of the SVC (18) during only a minor fraction of the fundamental cycle to prevent damage to the solid state devices (21) and the capacitors (20) of the SVC (18), otherwise caused by resonant line conditions or large amplitude harmonics. This relatively short gate drive signal, in the presence of large amplitude harmonics, will force the solid state electronic components to turn-off prematurely. As a result, the capacitors (20) of the SVC (18) provide incomplete reactive power compensation. Feedback from a capacitor polarity circuit (31) is used to determine switched capacitor status at a specific instant in each cycle. A VAR correction controller (24), responsive to the feedback, executes a control scheme to account for incomplete reactive power compensation.</p> |
