发明名称 |
CIRCUIT ARRANGEMENT WITH A CIRCUIT UNIT SUCH AS A REGISTER MEMORY CELL, MEMORY ARRANGEMENT OR THE LIKE |
摘要 |
The description relates to a circuit arrangement with at least one circuit unit (20) containing several clock-controlled elementary memories (22), the clock inputs CLK of which are connected to a shared clock line TL. The clock signals Ts1-Ts7 going in the direction of data flow, to the clock inputs CLK of the elementary memories (22) are at least partly staggered in time so that any changes in the state of the relevant elementary memories (22) can be triggered at different times. |
申请公布号 |
WO9600965(A1) |
申请公布日期 |
1996.01.11 |
申请号 |
WO1995EP02394 |
申请日期 |
1995.06.21 |
申请人 |
SIEMENS NIXDORF INFORMATIONSSYSTEME AG |
发明人 |
ELMER, WERNER;MORRIS, EDWARD;REINER, ROBERT;ROMBACH, GERD |
分类号 |
G11C7/10;G11C19/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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