A test circuit of embedded arrays in mixed logic and memory chips

摘要

A test circuit (44) for embedded arrays in mixed chips, is provided wherein a control gate (44.1c to 44.Nc) is connected to a standard control signal (LT). According to the (LT) value, the test circuit (44) connects or isolates the memory unit (12.1) and the logic part (12.2,14) of the mixed chip. The test circuit (44) operates as a switch placed between the power supply rail of the logic part (46) and the power supply rail (48.1 to 48.N) of the memory unit (12.1). All the input gates (44.1a to 44.Na) are cross-connected to the power supply rail of the logic part (46), and each output gate (44.1b to 44.Nb) is connected to the corresponding power supply rail (48.1 to 48.N) of the memory unit (12.1). During the TEST mode of the chip, the value of the control signal (LT) turns off the test circuit (44), and the memory unit (12.1) is not supplied. The memory cells keep unselected, and the logic circuits network (14) is tested. The faulty chips are rejected. Then the value of the control signal (LT) is inverted, and the control gate (44.1c to 44.Nc) connects all the power supply rails (48.1 to 48.N) of the memory unit to the power supply rail of the logic part (46). Then the test sequence of the embedded array is performed. Faulty memory cells are replaced in case of repaired elements, otherwise faulty chips are rejected. Thus the manufacturing yield of the mixed chips is improved, and moreover SPQL of the shipped products is significantly decreased. $$