发明名称 |
Phase-locked loop device, oscillator, and signal processor |
摘要 |
A PLL device includes a VCO (10) forming a phase-locked loop and an amplifier (18) for outputting a phase change signal having phase function with respect to frequencies, a synthesizer (20) having a first input receiving an error signal (phase comparison signal) from a phase comparator (2) through an LPF (4) and a second input for synthesizing signals at the first and second inputs to output a synthetic signal, and a phase and amplitude changer (15) for changing the phase and amplitude of the synthetic signal to provide a phase and amplitude change signal to the second input of the synthesizer in response to the error signal, the synthetic signal acting as an oscillation signal of the VCO (10), whereby the PLL device has a small variation in free-running frequency and a wide lock range.
|
申请公布号 |
US5483559(A) |
申请公布日期 |
1996.01.09 |
申请号 |
US19940309984 |
申请日期 |
1994.09.20 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
YAMASHITA, HIROMITSU |
分类号 |
H04N5/14;H03L7/08;H03L7/099;H04N5/44;(IPC1-7):H03D3/24 |
主分类号 |
H04N5/14 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|