| 摘要 |
PCT No. PCT/FR92/00951 Sec. 371 Date Jun. 11, 1993 Sec. 102(e) Date Jun. 11, 1993 PCT Filed Oct. 9, 1992 PCT Pub. No. WO93/07621 PCT Pub. Date Apr. 15, 1993.A method of checking post-erasure contents of an erasable permanent memory containing an instruction register and an address register, the method including steps of writing an erasure-checking instruction word into the instruction register, and timing-out for a predetermined duration. The step of writing the instruction word to the instruction register also initiates the steps of opening of the address register, presenting a first address to the address register, iteratively reading the contents of the memory at the address indicated by the address register and incrementing the presented address until the entire memory has been checked, and closing the address register. A device for implementing this method includes a circuit for generating an address-transfer enable signal applied to the address register.
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