Compensated phase locked loop for generating a controlled output clock signal

摘要

A method and apparatus for generating a controlled output clock signal which is frequency and phase referenced to an input signal is disclosed. The compensation is programmable to allow an external source, such as a processor, to download a compensation factor to create a variable frequency phase locked loop. A separate programmable divider is downloaded with a complimentary value to adjust the varied frequency signal to the frequency of the input signal.