| 摘要 |
The apparatus is characterized in that a first buffer, an input terminal of a first NOR gate, a first A bus collision detecting circuit, a first B bus collision detecting circuit, and an A bus oscillation preventing circuit are connected to input an A bus delayed signal, in that a second buffer, an input terminal of a second NOR gate, a second A bus collision detecting circuit, a second B bus collision detecting circuit, and a B bus oscillation preventing circuit are connected to input a B bus delayed signal, in that an output signal of the B bus oscillation preventing circuit is subjected to control the output of the A bus delayed signal, in that an output signal of the A bus oscillation preventing circuit is subjected to control the output of the B bus delayed signal, in that an output signal of the B bus oscillation preventing circuit is inputted to the input terminal of the second NOR gate, in that an output signal of the A bus oscillation preventing circuit is inputted to the input terminal of the first NOR gate, in that an output signal of the first NOR gate is provided to an input/output terminal of the first buffer, and in that an output signal of the second NOR gate is provided to an input/output terminal of the second buffer.
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