| 摘要 |
The device comprises a multiplexer which locates the address of video memory by selecting address, a central processing unit which inputs addresses from an address generating unit or addresses from CPU itself to the address of RAM by the selection of a multiplexer, an unit which generates not only load or clear signals to the address generating unit but also synchronization clocks, vertical synchronization signals, and horizontal synchronization signals, and a buffer unit which inputs converted output signals. |
