Data line control of MISFET memory

摘要

The memory cells (5a-5d) are connected to a pair of data leads (CD0,CD1) carrying complementary signals of high or low levels.A data lead-potential setting circuit contains a MISFET lying between the data leads to limit the potential difference between the latter.The cell (e.g. 5a) flip-flops are made up from a pair of MISFETs (e.g. Q1,Q2) and load resistors (e.g. R1,R2), all the cells (5a-5d) being arranged in a matrix. Two other MISFETs (e.g. Q3,Q4) from a transfer gate. The gate electrodes of the latter serve as selective cell connectors while the drain electrodes (D) serve as a pair of input and output terminals