发明名称 VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS
摘要 <p>A method and apparatus for vertically interconnecting stacked silicon segments (36) is disclosed. Each segment (36) includes a plurality of adjacent dies on a semiconductor wafer. The plurality of dies on a segment are interconnected using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads (42) for external electrical connection points. Each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls (102) on each of the segments (36). After the segments are cut from the wafer, the segments are placed on top of one another to form a stack (112). Vertically adjacent segments (36) in the stack (112) are electrically interconnected by applying electrically conductive epoxy traces (130) to all four sides of the stack. The inwardly sloping edge walls (102) of each of the segments (36) in the stack (112) provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked.</p>
申请公布号 WO1996000494(A1) 申请公布日期 1996.01.04
申请号 US1995006884 申请日期 1995.06.08
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