Schaltungsanordnung mit einer mehrere taktgesteuerte Elementarspeicher enthaltenden Schaltungseinheit

摘要

The description relates to a circuit arrangement with at least one circuit unit (20) containing several clock-controlled elementary memories (22), the clock inputs CLK of which are connected to a shared clock line TL. The clock signals Ts1-Ts7 going in the direction of data flow, to the clock inputs CLK of the elementary memories (22) are at least partly staggered in time so that any changes in the state of the relevant elementary memories (22) can be triggered at different times.