发明名称 |
METHOD FOR PROTECTING NETLISTS PROVIDED FOR SIMULATION |
摘要 |
A design protection circuit for a logic circuit comprised of a counter for receiving clock pulses with the logic circuit and apparatus for resetting the logic circuit upon the counter counting a predetermined number of clock pulses, the predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function.
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申请公布号 |
CA2130239(A1) |
申请公布日期 |
1995.12.31 |
申请号 |
CA19942130239 |
申请日期 |
1994.08.16 |
申请人 |
PMC-SIERRA, INC. |
发明人 |
SMITH, GRAHAM B.;HUSCROFT, CHARLES K.;LITTLE, VERNON R. |
分类号 |
H03K19/003;(IPC1-7):H03K19/00 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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