| 摘要 |
<p>A four-quadrant multiplier using multiple input floating-gate MOS transistors is provided. It is based on the square law characteristics of the MOS transistor and can be realised with only four floating gate MOS transistors, two resistors and a current source. The four floating gate transistors are configured with their sources connected in common and biased by a single current source. Output is taken between two common drain connections. Each transistor has three control gates with two being provided for selected ones of the two input signals and one for a biasing signal (optional). Input signals can be connected to the control gates in either a differential or single ended configuration. In one application, a programmable synaptic cell for neural networks employs the multi-input floating-gate MOS four-quadrant analog multiplier. Varying of the neural weight connection strength of each synaptic cell is achieved by two possible methods. One method involves programming charges into or out of the primary floating-gate of the MFMOS devices associated with the multiplier. The other method is to configure the third input gate of each MFMOS device of the multiplier as another (secondary) floating-gate structure whereby charge can be programmed into or out of this secondary floating-gate structure, and its coupling area to the primary floating-gate would determine the neural weight. The differential output current is proportional to the product of the input signal and the programmed charge difference. In a natural extension, an array of individually programmable synaptic cells form a neural network.</p> |
