| 摘要 |
An arrangement comprising a controllable clock signal source (1), a decision circuit (8) for determining the polarity of a received biphase signal at two successive sampling instants in a single symbol interval, and a phase detector (35) with a first comparator (16) to compare the polarity samples at the two sampling instants with each other. The phase detector generates a control signal for adjusting the frequency and phase of the adjustable clock signal source (1) in response to the output signal of the first comparator. A second comparator (28) compares polarity samples at the same relative sampling instant in two successive sampling instants with each other. The second comparator (28) inhibits phase detector (35) in response to the output signal of this second detector. In the case of false synchronization, the output of phase detector (35) will continue to present the same signal value, so that automatically an adjustment is made of the instant of correct synchronization. This adjustment is carried out by a VCO (3) and/or phase shifter means (12).
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