| 摘要 |
A method for implementation of muti-port interleaved memory systems comprising any prime number P of memory modules each of which contains a power of two memory banks. Each memory bank comprises a power of two memory locations. In this method, sequential addresses are mapped into sequential memory modules, and the addresses mapped into a given module are mapped into distinct memory locations within the module without explicit and implicit operations of division by the prime number P. The method embodies families of functions any one of which can be used for the bijective mapping of addresses into memory locations within a memory module. Furthermore, any of the functions is computable in O(1) gate delays employing O(log2P) logic gates. A multi-port interleaved memory system with P memory modules can serve multiple requests for vectors of data, where each memory port is used to serve a request for a vector of data. Disclosed is also a method for generating memory addresses for words of a vector in optimized address sequence of the alpha -type, where alpha is a fixed integer in the range 1</= alpha </=P-1. Serving a request for a vector of data at each memory port by accessing words of the vector in optimized sequence of the alpha -type minimizes memory access conflicts among the concurrent access of multiple vectors when the value of alpha is fixed at the same value for all memory ports.
|
