发明名称 |
Cascaded VLSI neural network architecture for on-line learning |
摘要 |
High-speed, analog, fully-parallel and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware-compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A computation-intensive feature classification application has been demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as application-specific-coprocessors for solving real-world problems at extremely high data rates.
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申请公布号 |
US5479579(A) |
申请公布日期 |
1995.12.26 |
申请号 |
US19940316711 |
申请日期 |
1994.09.22 |
申请人 |
THE UNITED STATES OF AMERICA AS REPRESENTED BY THE ADMINISTRATOR OF THE NATIONAL AERONAUTICS AND SPACE ADMINISTRATION |
发明人 |
DUONG, TUAN A.;DAUD, TAHER;THAKOOR, ANILKUMAR P. |
分类号 |
G06N3/063;(IPC1-7):G06F15/18 |
主分类号 |
G06N3/063 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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