Level conversion circuits for converting a digital input signal varying between first and second voltage levels to a digital output signal varying between first and third voltage levels

摘要

A level converts circuit converting a digital input signal varying between a first (VSS) and a second (VDD1) voltage level to a digital output signal varying between the first (VSS) and a third voltage. (VDD2) the local conversion circuit includes between first (VDD2) and second (VSS) poles of a DC supply source a series connection of a load impedance (P2/P3/N3) and the main paths of a first transistor (N2) and of a second transistor (N1), to a control electrode of which the input signal is applied. The first and second transistor are of a same first conductivity type. A third transistor (P1) of a second conductivity type is connected in parallel with the second transistor (N1). A control electrode of the third (P1) and first (N2) transistors are biased by a constant DC bias voltage (VBIAS1A/VBIAS1B), and a junction point of the load impedance (P2/P3/N3) and the series connection being an output terminal (OUT) of the level conversion circuit.