| 摘要 |
<p>PURPOSE:To reduce power consumption and to accelerate a response at the same time by selecting an internal clock signal based on the designation information of an operating frequency to be changed out of plural internal clock signals while being interlocked with an operation inside a module. CONSTITUTION:The module is composed of peripheral circuits such as a CPU 1 of the processor of a software, memory 2 and timer 3. A clock generating circuit (CPG) 4 outputs a reference clock signal 9 to be used for generating the plural internal clock signals at the respective modules. The changing command of the operating frequency is transmitted to all the modules as the object of an operating frequency change, and any designated module fetches the information of the operating frequency to be changed, selects the internal clock signal based on the designation information of the operating frequency to be changed out of the plural internal clock signal at good timing while being interlocked with the operation inside that module and changes the internal clock signal to be used inside the module.</p> |
