| 摘要 |
PURPOSE:To allow the circuit to cope with an input over a wide frequency range by extending the variable range of a clock frequency so as to extend the lock range of a PLL. CONSTITUTION:A phase comparator 11 compares the phase of a reference signal (3) and the phase of a comparison signal (5), its output difference signal is integrated by an LPF 12 and the output voltage of the LPF 12 is used to control a clock frequency oscillated by a VCO 1. The clock output of the VCO 1 is multiplied/divided to be a multiple of M/N at an M/N 21, which provides a system clock (4) as an output. The system clock (4) is frequency-divided by a frequency division counter 13 to obtain a comparison signal (5). A multiplication ratio M/frequency division ratio N of the M/N 21 is varied by a required signal for varying the multiplication ratio M/frequency division ratio N. Furthermore, a frequency comparator 22 counts the number of sampled system clocks (4) for 1H period of a sample control signal (6) from a control section 23 based on a signal to be processed and compares the count with that of the reference signal (3) and controls the M/N 21 based on a difference signal (7) to provide the output of the system clock (4) synchronously with the reference signal (3). |
