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发明名称
LATCH EMBEDDED LOGIC CIRCUIT AND METHOD FOR SPEEDING UP OPERATION THEREOF
摘要
申请公布号
JPH07334540(A)
申请公布日期
1995.12.22
申请号
JP19940125596
申请日期
1994.06.07
申请人
NIPPON TELEGR & TELEPH CORP <NTT>
发明人
MIYAZAKI TOSHIAKI;NAKADA HIROSHI;TSUTSUI AKIHIRO;YAMADA KAZUHISA;OTA NAOHISA
分类号
G06F17/50;(IPC1-7):G06F17/50
主分类号
G06F17/50
代理机构
代理人
主权项
地址
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