| 摘要 |
<p>PURPOSE:To improve the high speed performance and noise resistance by constituting a data sense circuit by using a clock synchronization type sense amplifier of two systems operating in time-division mode. CONSTITUTION:Address data is fetched in address latches 111a, 111b of two systems alternately in time-division made at falling timing of a clock CK, and alternately selected by a selector 12 at rising timing of the CK and taken out. A word line and a bit line of a memory cell array 101 are selected by an address taken out by the selector 112. Bit line data is alternately read out by sense amplifiers 113a, 113b of two systems in time-division mode at rising timing of the CK, and alternately selected by the selector 114 and outputted. Thereby, during one side of sense amplifiers outputs data, the other sense amplifier reads out data of the next cycle, and the high speed performance and noise resistance can be improved.</p> |
