发明名称 MOS FOUR-QUADRANT MULTIPLIER
摘要 PURPOSE:To realize a MOS four-quadrant multiplier which is formed in a semiconductor integrated circuit with a linear input voltage range. CONSTITUTION:The positive phase of a second input signal V2 is inputted to one of two-quadrant multipliers with the first input signal V1 as a common input and an opposite phase V2' is inputted to the other two-quadrant multiplier. The four two-quadrant multipliers are constituted as shown in the figure and a result with good linearity is outputted in accordance with the polarity of the two signal inputs.
申请公布号 JPH07334592(A) 申请公布日期 1995.12.22
申请号 JP19940130469 申请日期 1994.06.13
申请人 NEC CORP 发明人 KIMURA KATSUHARU
分类号 G06G7/163;(IPC1-7):G06G7/163 主分类号 G06G7/163
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