| 摘要 |
PURPOSE:To provide a PLL circuit having a wide pull-in operation range implementing automatic pull-in synchronization in following adaptively to plural input reference signals whose frequencies differ from each other. CONSTITUTION:In the PLL circuit consisting of a phase comparator 102 detecting a phase difference between an input reference signal 101 and a feedback signal 106 and providing the output of a signal corresponding to the phase difference, a low pass filter 103 receiving the signal corresponding to the phase difference, converting it into a DC voltage and providing the output of the converted voltage, a voltage controlled oscillator 104 controlled by the DC voltage fed from the low pass filter to generate a prescribed output clock signal, and a frequency divider 107 frequency-dividing the output signal to provide the output of a feedback signal, a variable frequency divider capable of frequency division operation at plural frequency division ratios is adopted for the frequency divider and the frequency division ratio of the frequency divider is selected equally to ratio of the oscillated frequency of the voltage controlled oscillator of the PLL circuit to an input reference frequency. |
