| 摘要 |
PURPOSE:To accelerate the processing of an arithmetic circuit and to reduce power consumption especially at a low voltage circuit in a highly integrated logic LSI. CONSTITUTION:Concerning a multiplier circuit for which a multiplier 1 and a multiplicand 2 are inputted and a multiplier output 3 is outputted, adder arrays 9 and 11 with small load capacitance and high-speed operations are composed of high-speed CPL circuits, and an input buffer 4 for multiplier, input buffer 5 for multiplicand, full scale detection circuit 6, booth encoder 7, booth decoders 8 and 10 and output buffer 12 are composed of CMOS circuits with small power consumption. On the other hand, this circuit is constituted by dividing the booth decoders 8 and 10 and the adder arrays 9 and 11. Therefore, the multiplier circuit can be accelerated. Especially, the power consumption of the entire circuit at the time of a low voltage can be reduced similarly to the conventional circuit entirely composed of the CMOS circuit and at the same time, an effect to reduce the deceleration of operating speed is attained. |
