发明名称 AUTOMATED SAFESTORE STACK GENERATION AND MOVE IN A FAULT TOLERANT CENTRAL PROCESSOR
摘要 <p>A fault tolerant central processing unit having data manipulation circuitry (60) including a plurality of software visible registers (61, 62), a shadow set (50) of the software visible registers is provided for use in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected.</p>
申请公布号 WO1995034855(A2) 申请公布日期 1995.12.21
申请号 US1995007012 申请日期 1995.06.02
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