The buffer includes NMOS and PMOS transistors, a data input and output contact layer, and an N-depression guard ring. The NMOS transistor is formed in a P-depression of an N-doped substrate and contains two N+ regions coupled to the drain electrode. The PMOS transistor is formed in an N-depression of a P-doped substrate and contains two P+ regions coupled to the drain electrodes. Both transistors have gate electrodes. To the second N+ region and first P+ region is coupled the data input and output contacting spot. The N-depression protective ring is between the P- and N-depressions and is separated at a certain spacing from the two depressions.
