| 摘要 |
<p>A flash memory chip (320) that can be switched into four different read modes is described. Computer systems (100, 200, 300, 800, 1300, 1500) and hierarchies that exploit these modes are also described. In the first read mode, asynchronous flash mode, the flash memory (130) is read as a standard flash memory. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip (320) and a series of addresses belonging to a data burst are specified, one address per clock tick. In the third read mode, asynchronous DRAM (dynamic random access memory) mode, the flash memory (130) emulates DRAM. In the fourth read mode, synchronous DRAM mode, the features of the second and third modes are combined to yield a flash memory that emulates a synchronous DRAM.</p> |
