发明名称 |
Failure tolerant memory device, in particular of the flash EEPROM type |
摘要 |
Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults. <IMAGE>
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申请公布号 |
EP0686979(A1) |
申请公布日期 |
1995.12.13 |
申请号 |
EP19940830283 |
申请日期 |
1994.06.10 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
CAMPARDO, GIOVANNI;CAMERLENGHI, EMILIO |
分类号 |
G11C17/00;G11C16/06;G11C16/34;G11C29/00;G11C29/04;G11C29/12;G11C29/50;H01L27/00;(IPC1-7):G11C29/00;G06F11/20 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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