| 摘要 |
PURPOSE:To reduce the jitter of an output clock signal by frequency-dividing a reference clock signal supplied from outside by a frequency dividing circuit, frequency- dividing a standard clock signal by an output clock frequency dividing circuit, and supplying both of the obtained frequency dividing signals to a phase comparison circuit through a window generation circuit for comparing phases. CONSTITUTION:This digital PLL circuit is provided with a frequency dividing counter 17 for preparing the output clock signal, a reference clock frequency dividing circuit 11 for frequency-dividing the reference clock signal and the output clock frequency dividing circuit 12 for frequency-dividing the output clock signal so as to detect the phase difference between the output signals of the circuits 11 and 12 by way of the window generation circuit 13 for comparing phases by the phase comparing circuit 14. When setting a frequency dividing value by a frequency dividing value setting circuit 16, one of a stationary value, a value obtained by subtracting a fixed minute quantity from the stationary value and a value obtained by adding a fixed minute quantity to the stationary value is selectively set counter 17. A frequency dividing value changing period for changing the value by the counter 17 to the minute quantity subtracted value or the minute quantity added value is generated by a frequency dividing value changing period generation circuit 15. |
