| 摘要 |
<p>PURPOSE:To secure a startup stable time at the time of resonator operation, and to eliminate an unnecessary oscillation time at the time of external clock supply operation and improve response by controlling the operation of a clock generating circuit with the signal outputted from a flip-flop. CONSTITUTION:The signal 103 outputted from the flip-flop 1 and the underflow signal 107 outputted from a counter 4 are inputted and a signal 108 is outputted and inputted to the clock generating circuit 6 and an OR gate 7. The operation of the clock generating circuit 6 is controlled with the signal 108 and the resetting of a counter 4 is controlled. The clock generating circuit 6 inputs the clock signal 104 outputted from an oscillation circuit 2 and outputs specific clock signals 109 and 110 on the basis of the clock signal 104. Consequently, the startup stable time at the time of resonator operation is secured and the unnecessary oscillation stable time at the time of external clock supply operation is eliminated to improve the responsiveness.</p> |
