| 摘要 |
PURPOSE:To shorten pull-in time at the time of step-out without deteriorating a jitter suppression characteristic at the time of phase synchronization by varying the loop characteristic of a phase synchronization loop in a phase synchronization circuit using an up-down counter. CONSTITUTION:In a phase synchronizing state the address of a FIFO memory 2 has a value near a half full flag*HF so that both of a full flag*FF and empty flag*EF come into a level H. At this time, the output of a negative logical NOR gate 12 comes into a level L, and the frequency dividing ratio of variable frequency dividers 3 and 4 becomes N. Thus, the cut-off frequency of the phase synchronizing loop in the phase synchronizing state does not change and the jitter suppression characteristic is maintained. On the other hand, in the state of the step-out of frequency synchronization, the full flag*FF or the empty flag*EF comes into the level L so that the output of the negative logical NOR gate 12 comes into the level H and the frequency dividing ratio of the variable frequency dividers 3 and 4 becomes (n). Thus, the loop gain K of the phase synchronizing loop is increased by N/n times so as to execute pull-in operation at high speed to reduce a pull-in time. |
